3D Chiplet Engineer✦ anywhere

About Us : AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.

Why Now : After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:

We are looking for a 3D Integration / Chiplet Expert to define and implement 2.5D/3D advanced packaging solutions for our Vertical Integrated Memory (VIM) technology. You will collaborate across teams to define optimal interconnect strategies and die stacking approaches to enable high-bandwidth, low-power operation. This job sits at the intersection of SoC architecture (specifically the physical design) , package design, and 3D manufacturing processes.
Key Responsibilities:

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Integration Architecture & Process Definition :
Develop and define architectures for 2.5D/3D stacking of VIM chiplets with compute chiplets.
Collaborate with design and technology teams to develop interconnect solutions that ensure high bandwidth and low latency.
Define clearly the impact of the chiplet physical design chiplets (through-silicon vias, micro-bumps, hybrid bonds, redistribution layers, and chiplet interfaces, …)
define fabrication flows and design rules with foundries, packaging partners, and internal physical design teams

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Performance Analysis & Simulation: Conduct early multi-physics simulations (thermal, electrical, mechanical) to analyze and optimize the performance and reliability of integrated systems.
drive external partners for final package design

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Collaboration & Communication:Partner closely with design, process engineering, metrology, and system architecture teams.
Participate in conferences, standardization bodies and industry events to promote or lead discussions about the future of chiplet integration.

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Technical Leadership:Provide
technical leadership and project management guidance to multidisciplinary teams.

About the team:

This role is part of the Product & system team, partnering closely with our cross-functional engineering teams in Product & system and Memory Design. We foster a highly collaborative, inclusive environment where strong alignment, high transparency and seamless team coordination are central to our shared success.
Requirements
About who you are:

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You’ve spent 5–10 years exploring the frontiers of 2.5D/3D packaging and heterogeneous integration, turning complex ideas into manufacturable systems.

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You have a deep understanding on the SoC physical design, TSVs, Redistribution Layers, hybrid bonding and how they are used at system level to implement chip IOs (Functional and power IOs)

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You are mastering Integrity 3D-IC Platform to define the chiplets interface, to define 3D stacking system, to generate the 3Dblox views, and to run all the 3D system level analysis (Power Delivery Network, Thermal, STA, LVS, SI/PI, …)

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You thrive where architecture meets technology — translating ambitious concepts into elegant, high-performance designs.

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Multi-physics isn’t just theory to you; you use thermal, electrical, and mechanical simulations to see the whole system clearly.

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You’re naturally collaborative — just as comfortable in technical deep dives as you are building bridge