Principal Modem PHY IP Design Engineer - Terawave

🏢 Blue Origin · all Blue Origin jobs
📍 United States
💰 USD 269,175 - 376,843.95 / annual
📅 Posted 2026-07-29 · via Himalayas
🏷 Modem-PHY-Design,Wireless-Communications-Engineering,ASIC-Design,Digital-Signal-Processing-(DSP),Hardware-Engineering,Associate-Principal-Wireless-Engineer,Principal-ASIC-Design-Engineer,Principal-Wireless-Network-Engineer
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Application close date:
Applications will be accepted on an ongoing basis until the requisition is closed.
At Blue Origin , we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! 
Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.
We are seeking a Principal Modem PHY IP Design Engineer to support the design and development of advanced modem physical layer (PHY) IP for the Terawave program. This role will contribute to the architecture, modeling, implementation, integration, and validation of modem PHY functions for next-generation high-performance wireless ASIC solutions.

The ideal candidate brings strong technical depth in digital communications and modem design, along with hands-on experience translating algorithms into implementation-ready hardware architectures. This engineer will work closely with systems, ASIC, RF, verification, FPGA, firmware, and validation teams to deliver robust and efficient PHY IP.
Responsibilities

· Design and develop  modem PHY IP  for Terawave ASIC and prototyping platforms.

· Contribute to PHY algorithm development and hardware architecture for functions such as:
omodulation and demodulation
otiming and frequency synchronization
ochannel estimation and tracking
oequalization
oFEC integration
oMIMO / beamforming support

oimpairment mitigation and calibration support

· Translate system and link requirements into  implementation-ready PHY block specifications .

· Develop floating-point, fixed-point, and bit-accurate models for modem PHY functions.

· Perform performance analysis and trade studies across throughput, latency, area, and power.

· Work with architecture and RTL teams to partition algorithms into efficient hardware implementations.

· Support interface definition and subsystem integration for PHY IP within the broader modem/baseband architecture.

· Collaborate with verification teams to define test strategies, reference models, and coverage plans.

· Analyze simulation, emulation, FPGA, lab, and silicon data to debug design issues and improve PHY performance.

· Support bring-up and validation of modem PHY features in FPGA prototypes and silicon.

· Document design assumptions, architecture decisions, performance results, and implementation details.

· Work effectively with internal teams and external design partners to help drive execution.
Minimum Qualifications

· Bachelor’s degree in Electrical Engineering, Computer Engineering, Applied Mathematics, Physics, or related technical field.

· 10+ years of experience in wireless communications, modem PHY design, DSP, or ASIC/FPGA-based baseband development.

· Strong background in  digital communications theory  and modem implementation.

· Experience in several of the following areas:
oOFDM and/or single-carrier systems
osynchronization algorithms
ochannel estimation and equalization
oadaptive modulation and coding
oFEC such as LDPC, Polar, Turbo, or BCH
ofixed-point analysis and quantization
oMIMO or beamforming techniques

· Proficiency with  MATLAB, Python, C/C++ , or similar tools for modeling and simulation.

· Experience translating algorithms into hardware-oriented architectures for  ASIC or FPGA  implementation.

· Strong analytical, debugging, and problem-solving skills.

· Ability to work across cross-functional teams in a fast-paced development environment.
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