Emulation Engineer, Lead
About Positron AI
Positron.ai specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.
About the role
As a Lead Emulation Engineer , you will provide technical leadership for the pre-silicon validation of Positron.ai ’s next-generation AI inference ASIC. You will own the end-to-end emulation strategy on the Cadence Palladium platform—architecting complex model builds, managing multi-rack partitioning, and driving the 'left-shift' of our software development. You will collaborate across RTL, DV, and Software teams to build high-performance virtual environments that prove out architectural functionality and accelerate firmware/OS bring-up months before tape-out. This role is critical to our silicon success: you will set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure our design is silicon-ready.
What you'll do
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Massive-Scale Model Architecture: Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
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Software Enablement (Left-Shift): Create and maintain the hybrid emulation and co-simulation environments (using SCE-MI or DPI ) that allow our software teams to boot OS images and run AI workloads on pre-silicon hardware.
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Full-Stack Validation: Design and execute comprehensive emulation test plans to verify high-speed interfaces ( PCIe Gen 6/7, 112G+VSR, Ethernet ) and complex AI memory hierarchies.
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Performance & Power Analysis: Utilize Palladium’s Dynamic Power Analysis (DPA) and throughput monitors to identify "true peaks" and performance bottlenecks that simulation cannot capture.
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Vendor Management: Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage the latest Palladium Z3 capabilities.
You'll Be Successful Here if You Have
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Deep Palladium Expertise: Extensive hands-on experience with Cadence Palladium (Z1/Z2/Z3) , including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
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Complex SoC Background: A track record of emulating multi-billion gate designs where partitioning, runtime predictability, and compile efficiency were critical success factors
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Automation Mastery: Expert-level Python , Tcl , and Bash skills to build and maintain the infrastructure for automated model releases and nightly regressions
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Hardware-Software Debug Skills: Proficiency in debugging low-level firmware and kernel-level issues using Verdi , SimVision , and hardware-software co-debug tools
Minimum Requirements
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Education: BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
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Experience: 8+ years in ASIC Emulation or Verification, with significant experience on large-scale Palladium installations
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Technical Skills: Mastery of SystemVerilog , Verilog , and C/C++ for transactor development and reference modeling.
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Protocol Knowledge: Deep understanding of data center protocols including PCIe , DDR and AMBA AXI/NoC
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Compensation & Benefits
The base salary range for this role is $180,000 – $300,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI,