ASIC Physical Design Engineer, Principal
About Positron AI
Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Our first-generation ASIC, Asimov, is a cutting-edge accelerator targeting frontier AI workloads, with additional generations already underway.
Role Overview
Own physical implementation of Positron's AI accelerators from floorplanning through tapeout. Lead implementation methodology while partnering with RTL, synthesis, DFT, package, and backend design services to achieve world-class PPA.
Key Responsibilities
Physical Implementation Ownership
- Own floorplanning, macro placement, and power planning across Positron's AI accelerator designs.
- Drive clock tree synthesis, place and route, and routing optimization through to timing closure.
- Own signal integrity, IR/EM closure, ECO implementation, and metal fill to deliver signoff-quality results.
- Own tapeout signoff for all physical implementation deliverables.
Methodology Development
- Develop methodology for power grids, power/ground tiles, and bump planning.
- Build congestion analysis and wire estimation approaches to support early floorplan decisions.
- Define partitioning and hierarchical implementation strategies for complex, multi-block designs.
Tools & Technical Ownership
- Own Innovus-based implementation flows end to end.
- Apply hands-on expertise across Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre.
Closure & Signoff
- Drive closure across timing, power, area, congestion, DRC, LVS, EM, IR, and yield.
Cross-Functional Partnership & Reviews
- Partner closely with backend design services to align on implementation strategy and execution.
- Review implementation quality and lead implementation reviews across the team.
AI-Enabled Engineering
- Apply AI-enabled techniques for automated QoR analysis, congestion prediction, routing prediction, and floorplan optimization.
Required Qualifications
- 12+ years of experience in physical design, spanning floorplanning through tapeout.
- A proven track record across multiple advanced-node tapeouts.
- Expert-level proficiency in Innovus and ICC2 implementation flows.
- Deep expertise in physical implementation, including floorplanning, clock tree synthesis, timing, and power closure.
- Hands-on experience driving full signoff across timing, power, and related quality metrics.
Preferred Qualifications
- Experience with AI accelerator design.
- Familiarity with large SRAM arrays.
- Experience with SerDes and LPDDR interfaces.
- Exposure to chiplet architectures and 2.5D advanced packaging.
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
What Success Looks Like
Success in this role looks like predictable implementation execution and excellent QoR across Positron's designs, paired with reduced schedule risk and a scalable implementation methodology that can support the company's growing portfolio of AI accelerators.
Why Join Us?
- Shape the physical implementation methodology for a new class of AI inference accelerators from the ground up.
- Work at the cutting edge of advanced-node design, tackling some of the hardest problems in power, timing, and signal integrity for frontier AI workloads.
Compensation & Benefits
The base salary range for this role is $150,000 – $300,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the rang